As the large file upload to download the channel,
This is the download link: book details AltiumDesignerWinter09 the basic functions, methods of operation and practical application skills. Author of the book collection more than a decade of experience in PCB design and practical work in the teaching of the experience in one, from a practical application, the typical case-oriented, task-driven, easy to understand introduction to AltiumDesigner software design environment, schematic design, schematic design level, multi-channel design, printed circuit board (PCB) design, three-dimensional PCB design, PCB constraints and validation rules, interactive layout, schematic libraries, PCB library, the library created an integrated circuit design and simulation, Protel99SE and AltiumDesigner conversion and other related technical content. This book is comprehensive, illustrated, easy to understand, practical, intuitive, not only as a vocational electronics, electrical, computer, communications and other related professional materials, you can also engage in electronic circuit design as a scientific and technical personnel to learn and reference books. – Book catalog] [Chapter 1 Introduction Chapter 2 AltiumDesignerWinter09 software knowledge to draw multi-vibrator circuit diagram in Chapter 3 Figure multivibrator PCB design to create schematic Chapter 4 Chapter 5 No device library components package Chapter 6 of the library to create the schematic drawing of the environmental parameters and set the way Chapter 7, the digital display circuit schematic drawing in Chapter 8 of PCB editing environment and parameters in Chapter 9 of the digital display circuit interactive PCB design Chapter 10 style layout and PCB design skills Chapter 11 level schematic and PCB design output file Chapter 12 Chapter 13 Chapter 14 of the circuit simulation and Protel99SE AltiumDesigner conversion References

1, the knowledge requirements:
requires students to master the understanding of digital, analog circuit based on the master circuit schematics, PCB board design, understanding of relevant concepts, understanding of circuit simulation, familiar AltiumDesigner software used for future work to lay a solid foundation.
2, skills and ability requirements:
through this course, requiring students to proficiency AltiumDesigner software design environment, schematic design, schematic design level, multi-channel design, printing circuit board (PCB) design, three-dimensional PCB design, PCB constraints and validation rules, interactive layout, schematic libraries, PCB library, the library created an integrated circuit design and simulation, Protel99SE and AltiumDesigner conversion and other related technical content. Learn how to use the software to solve the various problems in circuit design, multi-master a skill for the future of the graduate design work to lay a solid foundation.
.
Download: AD9-based tutorials. pd

Altium Designer v10.0.iSO-co2.17GB for more information
genre:
atomic program is designed for electronic components, fundamentalbuilding block. Drag and drop the ball with the components and the entire projectcomes stopped. With newer, more interesting products, or products, to make more creative use of ofcomponents with endless, growing demand and the market for new partsappearing interesting almost every day, it can quickly beoverwhelming try to keep upa ? much less maintenance and construction assists to maintain the project and supply chainintelligence which need to select the right partners to the top. Easy, 90 finished component panels wrapped in your choice of% of the cost, thepressure to get it right never greater.Enter Altium ? Next-generation element management Systema? The framework you need to manage the level of technology components, in design, the design and distribution areas. It extendsexisting store and manage data to the ECAD component capturethe engineering and business intelligence, and now need to make real senseof management component of engineers and designers face daily challenges eachand model. The new system includes.
A new component model to capture the intelligence behind the selection of some of
AltiumDesigner 1910 launched a new, higher componentobject level model, the separation from the manufacturer or vendorparts Engineering part of it. It does this by first choice, can be mapped to one or more manufacturers or vendorparts of engineeringcomponent series. Making it possible to capture partsequivalents a real concept behind, and take advantage of intelligent engineering thedecisions experienced engineers to make every day.
where a powerful new system to track the use of the design or release of any document components
AltiumDesigner 10 of the new system will eventually bring together componentinformation vault and library design data, and release it usethose components. This powerful new system makes it possible to trackwhere any component may be in any design.
powerful revision and lifecycle management capabilities to individual parts and components model level
AltiumDesigner 10 provides a comprehensive revision and lifecycle managementcapabilities, this approach extends to all components and evenindividual components model. With AD10 You can finally build your partsrevisioning and approval procedures, direct access to your designenvironment .
a component of the new life is connected to the supply chain system
AltiumDesigner 10 new live together suppliers to maintain a real timelinks systems, supply chain, and provide real-time updates of changes occure at any price information andavailability along the stage.
Installation
1. Extract
2. Burn / Mount
3. Installation
4. Lic file from the HS to the application directory directory
5. Run the application directory patch
Note: This is the final version of the Altium Designer (10.391.2208 4 all plug-ins and all appropriate licensing AD10todayavailable

AltiumDesigner use tips
just unfinished piece of circuit board, nothing else, trying to AltiumDesigner software used in some of the tips to share with you, hope you are not the place to be excused and corrected. As follows:
a multi-pin integrated circuit chip package SOIC, SOP, TSOP components in AD7.1 package library name meaning.
For example: SOIC library is divided into L, M, N of three.
L, M, N – on behalf of the chip after chip removal of the body width of the pin, that pin pad relative to the two chips minimum width. Where L is the width of the maximum, N times, M min.
– Select the name of SOIC_127_M where a group of packages, for example, select the named SOIC127P600-8M restructuring package.
which, 127P – on behalf of the same row as the adjacent pitch 1.27mm;
600 – two representatives of the chip relative to the maximum width of the pad pin 6.00mm;
-8 – - represents a total of eight pin chip.
Second, the package database, meaning the package called DPDT (Double Pole Double Throw), Similarly there is a package name SPST, DPST, SPDT;
Third, the software in the background of the circuit plate shape and the actual definition of the size of the mechanical layer 1 (regardless of radius) and large ways.
First, the PCB Board Wizard Custom in accordance with the actual size of an initial board (be sure to set the keepout reasonable spacing, typically 2mm). Then in the Edit-Origin for the board to set the origin of coordinates, the resulting board size set in the mechanical one layer, if you do not like the board afraid of hurting hands around the right angle, can be redefined as curved legs, and dimensions. All mechanical one layer selected circuit object of size constraints, and then select the Design-Board Shape-Define from select, circuit board form the background to complete the setting.
Fourth, some on Design-Rules setting skills.
1, if the design requires copper layer (and inner layer) and pad (either surface mount or through hole) of the connections connected thermal buffer, and deposited copper layer (and inner layer) and Via a direct connection is used to set the rules of method:
copper layer setting method:
projects in the rules found in the Plane Polygon Connect style project, the new subkey named: PolygonConnect_Pads, set where the first object matches as: (InPADClass ( ll Pads ), where the second object matches to: All; and select the connection type to connect to 45 degrees 4.
another new subkey named: PolygonConnect_Vias, set where the first object matches to: All, where the second object matches to: All; and select the connection type for the direct connection.
any of them in the sidebar to select a subkey, click the button to sit down and side Priorities will PolygonConnect_Pads child priority is set to the highest level and then shut down.
set within the layer method:
Similarly, in Power Plane Connect Style project, the new subkey named: PlaneConnect_Pads, set where the first object matches as: (InPadClass ( ll Pads ); connection type 4 connections.
another new subkey named: PlaneConnect_Vias, set where the first object matches to: All; the type of connection for direct connection.
any of them in the sidebar to select a subkey, click the button to sit down and side Priorities will PolygonConnect_Pads child priority is set to the highest level and then shut down.
2, deposited copper layer (copper layer of copper) and the alignment hole and the pad spacing methods:
Electrical projects in the new subkey named: Clearance_Polygon, set where the first object matches as: (IsRegion), where the second object matches to: All; and set the spacing is generally more than 20mil, 30mil appropriate.
3, deposited copper layer (copper layer deposited copper grid mode) and the alignment hole and the pad spacing methods:
need to go from the line spacing is set to 9,10 mil need copper spacing 30mil, and then deposited copper grid. Copper to be deposited after the end of the line spacing to go back to the original pitch, the system will not be the error.
five, with a copper layer and inner layer of more than four panels, in order to display circuit board layers, need to add layer standard, the use of digital identity on every level, will aim at the light at the standard level you can see the identity of each layer.
As the layer standard that needs to be light, so the region can not have any copper and the inner layer through. So, first draw a rectangle keepout layer, barrier layer through the upper and lower copper; then Place-Polygon Pour Cutout command at each layer within a rectangular box on the removal of regions that should completely overlap, with in the light; last layer in each layer placed on the appropriate standard characters.
six, larger chips in the next heat deposited copper mesh, copper and other regional deposition method:
keepout line fever or use of the chip wiring layer corresponding to areas prohibited (keepout layer) chip circle shape to;
deposited copper and then start the whole board to see the results, all copper heat-chip location no.
Note: the bottom of the chip but also all the ground vias is set to NoNet, do not let it ground! (So ??as not to apply copper when the chip is not the area near the keepout line has also been putting the copper.)
The next is to delete previous keepout layer draw a line;
following easy to handle, the same or copper, this time in the heat of the chip area is deposited copper mesh, do not worry, you can circle a large copper area to prevent copper incomplete chip area, even taking up the position to be deposited the copper, Copper or copper results.

How AltiumDesigner DDR, etc. to achieve two long traces 2011-04-15 16:14
shown to ARM, DSP and other SOC core electronic systems, there is often two or more DDR / DDRII SDRAM. Taking into account DDR / DDRII SDRAM operating frequency is generally higher than in the PCB layout when need to do isometric wiring to ensure DDR / DDRII SDRAM read and write timing. That contain two or more DDR / DDRII SDRAM system, where the requirements of equal length wiring has two meanings. Take ADDRESS signal is concerned, the meaning of the first layer of a request from a SOC to each pad of ADDRESS together DDR / DDRII SDRAM pad corresponding to the length between the same (A B = A C), the second layer of meaning ADDRESS SOC required of all the pad to the corresponding DDR / DDRII SDRAM to be of equal length between the pad (all A B = All A C).
but in Altium Designer, SOC of a ADDRESS pad and the corresponding DDR / DDRII SDRAM definition of the network between the pad is the only (that is, A, B, C have the same network name), network length is defined as (A B C), can not accurately know the A, B and C of length. Then how in Altium Designer to achieve DDR / DDRII SDRAM for so long wiring it?
Following a project DRAM_A0 ~ A3 four signal lines of equal length design, for example, introduced in Altium Designer , etc. to achieve DDRII SDRAM long wiring. U23 for the CPU, U7 and U8 for the two DDRII SDRAM. DRAM_A0 ~ A3 for the low four address signals.
following a project DRAM_A0 ~ A3 four signal lines of equal length design, for example, introduced in Altium Designer so long to achieve DDRII SDRAM wiring. U23 for the CPU, U7 and U8 for the two DDRII SDRAM. DRAM_A0 ~ A3 for the low four address signals.
First, the From-To Editor DRAM_A0 ~ A3 defined in the From To.
in the From-To Editor, select DRAM_A0, you can see DRAM_A0 three nodes on the network. Are U23-N12, U7-8 and U8-8. In the node list selected U23-N12 and U7-M8, and then click the button Add From To DRAM_A0 (U7-M8: U23-N12), generated DRAM_A0 first From-To. Then by the same method to generate a second From To, U23-N12 and U8-M8. (Shown as side two)
back to follow the same steps, in turn generating DRAM_A1 ~ A3 From To.
Second, add the class DRAM_ADD
From To From To Classes in, add a new name for the DRAM_ADD class, then DRAM_A0 ~ A3 are all From To add to this class. As shown below:
Third, find the longest alignment, so long as the wiring of the baseline.
listed first DRAM_A0 ~ A3 length of each net and all From To length. From To find the length of the longest-1944mil (For convenience of calculation, rounded), and the corresponding net-DRAM_A0-length 2263mil and another From To length 1587mil. Finally, according to the length of the three identified ADDRESS net basis of equal-length wiring.
L = 2263 1944-1587 = 2620 mil.
Fourth, the use of network length adjustment command, the U8-M8 in DRAM_A0 to U23-N12 From To (From To the shorter of two), the length of the net adjustment DRAM_A0 2620mil
five , DRAM_A1 ~ A3 to adjust the length of the net
DRAM_A1 two From To length are 1840mil and 1689mil, net length 2255mil. The first part of the public in DRAM_A1 (A), the adjusted net length 2359mil (2255 1944- 1840). Then in a short From To (1689mil), the adjusted net length 2510mil {[1944 - (1944 - 1840 1689)] 2359}
done in the same way to adjust the length of DRAM_A2 ~ A3.
VI: final results
From To length are each about equal to 1944mil, to achieve such long wiring. There is a slight difference is due to rounding the actual trace length caused
seven, DRC rule set
for the previously defined DRAM_ADD class, do the DRC parameter settings, mainly wiring length.
this route is declared completed so long.

I. Integrated Library Overview
AlTIumDesigner the concept of using an integrated library. Components in the integrated library not only has the schematic symbol representing the element, also integrates the corresponding function module. If FootPrint package, circuit emulation module, signal integrity analysis module. (Diagram shown in Figure 1) integrated library has the following advantages: easy to transplant and sharing integrated library, the connection between components and modules with security. Integrated library during the compilation process will detect an error, such as pin package corresponding to the other.
two.
create an integrated database to create an integrated library has the following main steps
1.) Creating an integrated library package
2.) increased component schematic symbol
3.) modules for the component symbols to establish connection
4.) compiling integrated libraries
example:
1. execute FileNewProjectIntegratedLibrary, create a wrapper library project, and then rename and save to the directory, such as c: librarylibrary, generate library.libpkg integrated library package.
2. in the project tab right-click project name in the pop-up menu, select add schematic libraries. (Figure 2) and name to save.
3. In shclib editing interface, select the Place menu tool to draw a component symbols, as shown in Figure 3, adding an NPN transistor.
4. schlibrary tab, select the default device name component_1, double-click into the component properties dialog box. In the “defaultdesignator” enter the default symbol name; (such as Q?) In the “comment” at the input of the component description; (such as NPNTransistor) in the “physicalcomponent” enter the name of the component; (NPN) Figure 4. Click OK to generate a component called the NPN.
5. symbol components to create modules for the connection before you set up search path. Choose ProjectprojectOption …, enter the project properties dialog box, add the module path in SearchPaths page. Footprint libraries AltiumDesigner6libraryPCB path. Look in order to prevent too large, the general “includesub-foldersinsearch” is not selected. Then click “refreshlist” button. Figure 5
establish Footprint module connection interface shclib click the lower left corner AddFootprint, add components into the package interface, use the Browse button to select the Cylinderwithflatindex.pcblib under BCY-W3 package. You can also use the Find button to find the required package. Click OK, so a good package module loading. Figure 6
build simulation module connected
AltiumDesigner spice model file format is *. ckt or *. mdl, directly from the component supplier website to download the corresponding model. In this case the model file in AltiumDesigner6examplesutorialscreatingcomponents directory to the directory onto “searchpaths” in. Similar increase in component packaging, choose “Addsimulation”, loaded pop-up dialog box, in the “modelkind” options “transistor”, in “modelname” type NPN, (corresponding with NPN.mdl file) in the “description” to add description. Click OK to add this module is a good simulation. Figure 7. If no spice model, you can choose “create …” button to manually add a model.
connection module to establish signalintegrity choose “Addsignalintegrity” Open dialog box, in the “type” at the choice “BJT” type, the other can choose the default values, you can also use “importIBIS” button to import the file model. Click OK. Above can increase the 3D model, 3D model file format is *. VRML, *. IGES.

Altium Designer is the following Protel Altium products (Protel99, Protel99SE, Protel DXP, Protel 2004) after the high-end design software, compared to the previous product development capabilities to enhance the FPGA. He board-level electronic product design, programmable logic devices and embedded design and development together, can be a single design environment to complete electronic design, through the Altium Designer software and the combination of NanoBoard development board, so the more rapid development and testing and effective. Meanwhile, Altium Designer also integrates modern design data management capabilities, making Altium Designer to become a complete electronic product development solution, can be described as both a meet current, but also to meet future development needs solutions. Compatible version of Altium Designer provides a previous version and new features.

AltiumDesigner in-circuit emulation and the steps 2010-10-13 AltiumDesigner circuit simulation is still very powerful, here is help inside “TU0106Defining

1. The floor of the copper pad and pin direct connection, do not thin connection.
looking for in the rules inside the plane, where there is one item PolygonConnectStyle, this option is set to copper connections, and the inside ConnectStyle into DirectConnect on it.
DXP, Protel99 settings and AltiumDesigner almost.
2. in the PCB Editor-Interactive Routing in the alignment can be restricted to 90/45 degree angle alignment, Restrict to 90/45, if not restricted, then use shift space corner styles available are:
* Any angle
* 45 °
* 45 ° with arc
* 90 °
* 90 ° with arc 3. impedance routing capabilities in Design \ Rules rules in which the width settings. Such as cloth impedance of 50 to the alignment of the haracteristic Impedance Driven tick the box in front, then the maximum, minimum and optimum impedance are set to 50.
4. bus routing function
1.Shift left mouse button to select the pad with the wiring (or segment);
2. Select the menu Place \ Multiple Traces, or the shortcut key “P” start wiring;
3. in accordance with a single route alignment manner.
4. If the wiring from the pad at the start, you can use “” and “.” key to shrink or spread out wiring. You can also click “Tab” key to set the two walking distance from the center line.

A circuit-based simulation and design software ① Pispice9.2 Spice-based simulation model, is recognized as the analog simulation tools, with simulation efficiency, and the actual results of close to 80%. But the toolbox of many, slightly more complex operation. ② Mutisum10.0 (also called EWbench) belongs to the National Instruments (NI). The software-based virtual instruments, and equipment range, all the simulation results based on realistic laboratory instrument interface presentation, feel very natural to operate, but rather with the design operation of the device is a very good tool for WYSIWYG , is the preferred software to learn analog circuit, in its latest 5.0 version has also joined the 8-bit microcontroller PCB design and simulation. ③ protel99SE entry-level circuit design tools, hardware engineers in China, most of it is definitely not new, the entire device is lean, mean, less than a full installation of the required hard disk space 300M, with a 1-2 layer PCB board design and simulation capabilities. Suitable for hardware circuit design EDA software as an introduction to use. ④ AltiumDesigner2009 AltiumDesigner software protel software upgrade, has gone through the 2004 and 2009 to the present, more powerful software, and now this software also has the FPGA design and simulation in C and HDL language ability, but it also changed protel more than huge, the installation file nearly 1.5 G, a complete installation of disk space occupied nearly 3G. Share of system resources when running a lot, at least 200M memory or more, is a huge count is a big thing. However, AltiumDesigner2009 has withstood so many upgrades, it is now still can not do the multi-layer high-speed PCB design, the final analysis is its high-speed signal integrity analysis and simulation capability is weak. Therefore, to design multi-layer high-speed PCB comrades should choose a professional or a number of tools such as Mentor and Cadence software. ⑤ CadenceAllegro16.2 this software for Cadence latest high-speed PCB design software, I was studying last semester, “High Speed ??Circuit Analysis and Design” This course is a little contact, only to learn its schematic drawing and PCB layout, It also has many other powerful features, very complicated. As the Allegro is developed under Linux, many of its operations and LINUX similar for people who are accustomed to Windows, just start feeling some will not meet. However, no relationship, it will slowly adapt to, after all, its high-speed circuit design is professional enough, strong enough, in large domestic companies to do hardware design almost without exception, the use of it, learn it is not employment worry Yeah, huh, huh! . Finally, the Allegro high-speed circuit design a lot of work has focused on setting rules on the placement and routing. Therefore, learning Allegro patience is essential. ⑥ Proteus7.4 (now the latest version is 7.6) Proteus Software is a class of Spice-based model and schematic design, system-level circuit simulation and PCB design-based EDA tools. It a powerful place to be on the microcontroller and its peripheral circuit simulation software. Which means it can invest without any hardware costs in the case before the entire digital and analog circuitry for hardware evaluation. This concept is undoubtedly innovative and practical. Proteus is currently supported by the simulation software, including most of the 51 single-chip MCU and the LPC ARM7 MCU. Terms of use from their own feelings, Protus has given me a fresh. But I hope it can continue to develop, support more of the MCU and peripheral digital analog simulation software. Expectations. Two, MCU design software ① Keil7.6 (ie uVision2) This software is designed to contact the first single-chip software, Keil, Germany finest creations, to support more than 90% of the 51 core chip, set 51 assembler (A51), C language compiler (C5), and 51 connectors and debugger in one, can be 51 assembly language, C language programming and debugging, the software can also be simulated using the interface is very friendly, simple, very practical. Actually learning the MCU of choice and the necessary entry. ② KeiluVision3 uVision3 is keil design products, an increase of 32 for the MCU support, mainly for ARM7/ARM9/Cortex series ARM chip assembly and C language programming and debugging. Use processes and consistent user interface and uV2, many companies are now developing ARM chip of choice. ③ ADS1.2 (upgrade version CodeWarrior4.x) ADS1.2 Motorola software, now it semiconductor division has been independent, as Freescale (freescale) semiconductor company, ADS1.2 for the ARM chip integrated development environment, junior year curriculum design do feel good when used. But its operation and software settings slightly more complicated than keil. As for the upgrade version CodeWarrior4.x it was freescale8 / 16 bit / 32-bit MCU integrated development environment. ④ IAR as IAR, is said to be the most outstanding MCU development tools, has a powerful, efficient compiled code, to support the MCU multi-species, etc., is to learn NEC78xx Series MSP430 microcontroller and TI16-bit microcontroller of choice for software design and compilation tools. Three, DSP design software, four, FPGA design software ① LiberoIDE8.3 (latest version LIbero8.6) LiberoIDE to ACTELFPGA design software. ACTEL FPGA is the Flash-based, power-down configuration information department lost power to run with high reliability and low cost, high security, low power consumption is widely used in aerospace, civil areas is less common, the within the integrated analog and digital FPGA IP blocks and 8051 nuclear. ② Quartus II4.2/5.1/6.0/8.0/9.0 for QuartusII this software, user interface is very friendly, integrated, including SOPCBuilder, DSP Bulilder, MegaCore, ProgrammerandSignalTapII other software, including many AlteraFPGA development and design tools. Which SOPCBuilder for its integration and embedded system hardware design tools and peripherals to complete NIOSII32bit IP or soft-core user module integration; DSP Builder design tool for the AlteraFPGA the DSP, you need to install the corresponding version of Matlab (such as the latest QuartusII9. 0 corresponds to the Matlab software version Matlab2008a or higher), its essence is in the Matlab Simulink tools added Altera FPGADSP design tool components, to achieve the floating-point tools to design fixed-point HDL hardware design; MegaCore to AlteraFPGA IP core cases of tools, IP cores can complete a variety of parameter settings and case-based work; and SignalTapII is Altera JTAG-based FPGA core and low-cost embedded logic analyzer, you can observe the FPGA internal and external to any signal (but take the FPGA on-chip RAM resources, RAM and observe how much the signal is proportional to the number and depth of storage) is very useful, is usually designed to solve AlteraFPGA essential tool for debugging problems. ③ NIOSIIIDE6.0/9.0 NIOSIIIDE is AlteraFPGA embedded soft-core 32bit-NIOSII software integrated development environment, using the popular gcc compiler supports the compilation of NIOS, C and C compiler, link, download and debug, is embedding learning based AlteraFPGA essential software system development. The entire software engineering document management clarity, the operation is very easy. ④ ISE8.2i/9.1/10.x/11.3 Needless to say that now XilinxFPGA in the market share of absolute advantage. As the ISE development tools it is notoriously good industry EDA software, it extremely efficient design, operation simple process. ISE also integrated and QuartusII as many of the Xilinx FPGA development of its own necessary tools, including IP generation tool CoreGenerator, timing analysis tool TimingAnalyzer, design constraints tool Constraints Editor, pin assignments and timing constraints tools Floorplan EditorandPACE, intelligent analysis tools SmartXplorer (LinuxOnly), mapping and place and route tools MAPandPAR, XilinxFPGA synthesis tool XST, ISE integrated simulation tool ISE Simulator (ISIM), Xilinx online debugging embedded logic analyzer ChipScopePro (as opposed to Altera SignalTapII) and XILINX Project Navigator ProjectNavigator etc. . ISE powerful logic function is designed to achieve XilinxFPGA essential tool. ISE brings users not only have more of a powerful and innovative concept. ⑤ EDK10.x/11.3 EDK for Xilinx embedded system design and development provides a strong software protection. XPS and SDK which includes two parts, corresponding to XilinxFPGA embedded system design system integration of hardware and software design. Currently, Xilinx Embedded own a total of three cores – 8bit-PicoBlaze, 32bit-MicroBlaze, and 32bit-PowerPC405/440. The first two of embedded soft-core, which is embedded hard-core. In XPS can be graphically intuitive to complete MicroBlaze and PowerPC core hardware design and a simple application engineering software design (including software, edit, compile, link, download and debug). Including cutting the kernel configuration and its connection with many peripheral IP, and XPS systems integration tools can also be tools to automatically generate the corresponding peripheral driver functions and the system board support package BSP, when quite convenient to use. SDK is XilinxFPGA advanced embedded system software design tools to support the operating system software with the edit, compile, link, download and debug. SDK is currently supported operating system Standalone, Xilkernel, Linux2.6 and third parties Vxworks. In addition, SDK XSP also automatically detect and update changes in hardware, making the SDK Xilinx embedded system software design as an ideal solution. ⑥ SystemGenerator10.x/11.3 SystemGenerator (referred to as Sygen) and Altera DSPBuilder, are based on Matlab and FPGA design software, the use of fixed-point floating-point tools to design the FPGA hardware. Must be installed before using Sygen ISE and its corresponding version of the Matlab software (such as ISE10.x support Matlab version Matlab2007a and Matlab2007b, and ISE11.x the support Matlab2008a or later). You can call in Sysgen Simulink software tools integrated XilinxDSP toolbox modules in a graphical way to achieve the FPGA DSP designs. Sysgen tool will automatically generate the ISE project, HDL language file and Modelsim simulation files. Note: Each model Sysgen design module must include a XilinxGenerator icon to set the project properties and call the ISE design tools to generate the netlist file (ngc) and so on. ⑦ ModelsimSE6.1/6.5 Modelsim of Mentor has introduced a powerful graphical simulation tool, is now recognized as the industry best EDA simulation tools. It supports a variety of FPGA devices (need to install the corresponding simulation library, because it comes with only a few commonly used in simulation libraries), VHDL and VerilogHDL hybrid simulation, and a variety of input methods and mode of operation can be analog in the form of Watch digital signal, is very easy to use, and powerful, we recommend using. ⑧ Synplify/SynplifyPro8.6/9.6.2 Synplify tool for the industry most professional EDA synthesis tools, to support a number of manufacturers of FPGA and CPLD devices and a variety of mixed-language input, can generate the corresponding RTL netlist file and view maps and logical use of resources situation, from my practical experience of using the Internet for people talking with its comprehensive and high efficiency is not inconsistent, can be optimized in a variety of integrated room, its software interface is also doing pretty well, very professional and practical . Fifth, system-level algorithm design software ① Matlab6.5/2007a/2008a (the latest version of the 2009b (download there) / 2010a (said it)) Matlab name believe that every engineering student, are not unfamiliar, it is based on the floating matrix operations points calculation tools, now it powerful mathematical ability has been widely used in the social production of various fields and disciplines and engineering fields. Tens of thousands of engineers around the world using Matlab. This point, you only need to look at it Simulink toolbox to know. ② Labview8.x (latest version Labview9.0) Labview is one of NI main software, which is based on graphical programming language – G language, creating a new electronic design and measurement methods. Now makes electronic engineers to complex programming languages ??from the hair freed to the system level with an intuitive graphical way, with the WYSIWYG view to engineering design and management. Its implementation based on Labview virtual instruments, the use of powerful PC functionality for data acquisition and measurement, low cost and flexibility to replace traditional instruments, I think this is bound to become the future of electronic measurement and instrumentation development trends. So, Labview is that we can learn a very powerful software. ③ PSoCDesigner5.0 This is Cypress (Chinese Cypress) the company PSoC development environment. The so-called PSoC that ProgrammableSystemonChip, programmable system on chip. PSoC concept put forward 90 years and 20 world, the development of microelectronics technology then becomes a hot spot, he integrated including MCU core, including analog and digital hybrid systems. Currently, Cypress PSoC3 series chip M8C core MCU, PSoC5 series chip Cortex32bitARMMCU, its wealth of programmable analog and digital peripherals including ADC, PGA, filter, comparator, DAC, PWM, Timer timer, UART , I2C, SPI, USB2.0 controllers, wireless transceivers.